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Staging Length Table - A Means of Minimizing Cache Memory Misses Using Variable Length Cache Lines

IP.com Disclosure Number: IPCOM000050034D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Driscoll, GC: AUTHOR [+4]

Abstract

In a computing system with a cache, when the CPU encounters a storage reference that cannot be satisfied by the cache (a demand miss), processing usually must be delayed for an access to main storage. Because of the increasing disparity between CPU and main storage speeds, the penalty for cache misses is both substantial and increasing in cycles per instruction. Therefore, one needs to forestall "demand misses" by bringing in a sufficiently long sequence of storage entries (which can be expected to be needed, because of locality of reference) while not bringing in too much, which might force out of the cache entries which will still be needed later.

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Staging Length Table - A Means of Minimizing Cache Memory Misses Using Variable Length Cache Lines

In a computing system with a cache, when the CPU encounters a storage reference that cannot be satisfied by the cache (a demand miss), processing usually must be delayed for an access to main storage. Because of the increasing disparity between CPU and main storage speeds, the penalty for cache misses is both substantial and increasing in cycles per instruction. Therefore, one needs to forestall "demand misses" by bringing in a sufficiently long sequence of storage entries (which can be expected to be needed, because of locality of reference) while not bringing in too much, which might force out of the cache entries which will still be needed later.

A "Staging Length Table" (SLT), a hardware table each of whose entries contains an address and a count, is described. When a cache miss occurs, the SLT is consulted. If the address in question is not found in the SLT, one line is transferred between main storage and cache, as usual. If it is found in the SLT, the count field indicates how many sequential lines are to be transferred, starting with the one referred to by the miss. In one possible version, a cache miss occurring during the transfer of several lines from a previous miss would cause the termination of that sequence after the current line transfer.

Entries are made in the SLT when a program is loaded (displacing the entries which refer to the part of storage b...