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Prestage Cache Lines of SVC Routines

IP.com Disclosure Number: IPCOM000050036D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Rechtschaffen, RN: AUTHOR

Abstract

Certain supervisor functions in current operating systems are invoked using an SVC instruction. The particular Supervisor function is designated as the parameter of the Supervisor Call (SVC), so that different functions are invoked by SVC0, SVC1, SVC2, etc. Cache simulations have shown that the initiation of an SVC significantly alters the contents of the cache. This means that a considerable amount of cache lines are loaded by the Supervisor function. The SVC routines also have a repetive I-fetch pattern. The "SVC n" causes a hardware interrupt on the IBM System/370, and this signal can be used by the hardware to trigger the mechanism discussed below.

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Prestage Cache Lines of SVC Routines

Certain supervisor functions in current operating systems are invoked using an SVC instruction. The particular Supervisor function is designated as the parameter of the Supervisor Call (SVC), so that different functions are invoked by SVC0, SVC1, SVC2, etc. Cache simulations have shown that the initiation of an SVC significantly alters the contents of the cache. This means that a considerable amount of cache lines are loaded by the Supervisor function. The SVC routines also have a repetive I-fetch pattern. The "SVC n" causes a hardware interrupt on the IBM System/370, and this signal can be used by the hardware to trigger the mechanism discussed below.

For each SVC the hardware maintains a linear array of Line Addresses and pacing information, as shown in the SVC instruction fetch table below.

An entry in the table will give the address of a cache line (i.e., LINEADDR #1,...,LINEADDR #M) and a pacing parameter Pi. The line address retrieved from the table will access the cache directory as if it had originated from the processor. This action serves to prestage the line to the cache before the processor requires that line. The timing of this cache access is controlled by the pacing parameter Pi (for the i/th/ line), which specifies one more than the number of cycles by which this access is delayed. A value of zero terminates the process. If the value of P(1)=0, this represents a situation where no line addresses have been input...