Browse Prior Art Database

Hardware Realization of Software

IP.com Disclosure Number: IPCOM000050041D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 30K

Publishing Venue

IBM

Related People

Roth, JP: AUTHOR

Abstract

Computers are composed of algorithms realized in hardware and algorithms realized in software. Because the cost of VLSI (very large-scale integration) hardware is precipitously decreasing, and because of speed considerations, the hardware-realization may be VASTLY faster than the software, a hardware realization might, in some instances, be attractive. A general form of REGULAR program and an algorithm compiler for transforming it into a very general form of REGULAR hardware are described herein. It is assumed that all arguments and values of functions are vectors with binary components. This compiler is a generalization of RTRAN (1) which transforms a high-level hardware specification into hardware. A rendition of this compiler was given in (2). A PRIMITIVE R-ALGORITHM is of the following form v=F(u)=:v1=F1(u1);...

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 40% of the total text.

Page 1 of 4

Hardware Realization of Software

Computers are composed of algorithms realized in hardware and algorithms realized in software. Because the cost of VLSI (very large-scale integration) hardware is precipitously decreasing, and because of speed considerations, the hardware-realization may be VASTLY faster than the software, a hardware realization might, in some instances, be attractive. A general form of REGULAR program and an algorithm compiler for transforming it into a very general form of REGULAR hardware are described herein. It is assumed that all arguments and values of functions are vectors with binary components.

This compiler is a generalization of RTRAN (1) which transforms a high-level hardware specification into hardware. A rendition of this compiler was given in (2).

A PRIMITIVE R-ALGORITHM is of the following form v=F(u)=:v1=F1(u1);...; vr=Fr(ur); ((a=1)=)v=>F(w)); (a=0)=>v=t where v is the primary output variable; F is the function performed by the primitive R-algorithm or subroutine; u is its argument; v1...., vr are the value-variables of the primitive functions F1....,Fr, and ul,...,ur are its respective arguments; a is a conditional variable (equal to 1 or 0) which decides whether or not the subroutine, primitive R-algorithm, is to be repeated, with different values for arguments, or not: if a=l, it is; if a=0, it is not. The w is the argument for F in its recursive segment, if a=0, then v has the final value t, as computed by the other functions, (the symbol => stands for IMPLIES).

The primitive R-algorithm is executed, in general. in parallel with respect to the functional dependencies between the arguments. For example, the conditional functional expression ((a=1)=>v=F(w)) is performed as soon as condition a (to be 1) and its argument w are determined.

It is assumed that there are standard hardware implementations for each of the F's, plus the interconnections determined by their topology. The only thing left to do in this hardware implementation is to implement the branch conditions: (al)=>v=F(w);(a=0)=>v=t; but this is easy to do in R-design. The first conditional statement gives the condition, namely, that a=1, under which the final output of the function is endowed with a value. On the other hand, the second condition (a=0)=)v=F(w) specifies a simple recursion for the overall function. For the first, there is a register in which is stored t whose contents are ANDed with (a=1); there will be an extra bit for control in the register to indicate that the answer t has been attained: this too will be ANDed with (a=1), and when this has the value 1, the product then the final answer for the algorithm execution will have been attained.

For the second conditional, a register is needed to store all the new arguments comprising w; similarly a register is required for the original value of u: the first is ANDed with (a=1), and the second, with (a=0). This completes the essentials for the hardware realization of the p...