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Anti-Contention Mechanism for Memory Access

IP.com Disclosure Number: IPCOM000050056D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Poret, M: AUTHOR

Abstract

This article relates to an anti-contention mechanism to be used in a microprocessor environment when adapters working in a memory-mapped I/O mode are used (that is, the adapters are considered by the microprocessor as memory. The adapters are on the memory bus of the microprocessor, and they also have to work from their own part.

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Anti-Contention Mechanism for Memory Access

This article relates to an anti-contention mechanism to be used in a microprocessor environment when adapters working in a memory-mapped I/O mode are used (that is, the adapters are considered by the microprocessor as memory. The adapters are on the memory bus of the microprocessor, and they also have to work from their own part.

The mechanism, as shown in Fig. 1, is more specifically designed for memory buffers accessed asynchronously in read/write mode by a microprocessor MP and synchronously by a counter CNT. The asynchronism of access to the buffers results in contention problems between the microprocessor and the counter.

It is assumed that the counter has to keep priority and cannot be stopped. Furthermore, the microprocessor tidings are not easily manageable.

Two buffers, as shown in Fig. 2, called ODD and EVEN, working in parallel with the same physical addresses, one being accessed by the microprocessor and the other accessed by the counter, are used.

A switching mechanism is implemented between these two buffers to keep the same information level inside them. The requirement is to duplicate each "write" order. The first order being addressed to one buffer (the ODD one, for example), the second order being addressed to the other buffer (the EVEN). The second "write" order is exactly the same as the first one because the buffers are at the same physical address and the microprocessor has knowledge of one buffer....