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OAI CMOS Circuit

IP.com Disclosure Number: IPCOM000050066D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+2]

Abstract

A complementary metal oxide semiconductor (CMOS) OR AND INVERT (OAI) circuit is provided which uses relatively few devices or transistors and which has a structure layout suitable for automated logic methodology.

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OAI CMOS Circuit

A complementary metal oxide semiconductor (CMOS) OR AND INVERT (OAI) circuit is provided which uses relatively few devices or transistors and which has a structure layout suitable for automated logic methodology.

The circuit, as shown in Fig. 1, having four inputs A, B, C and D, represents the function A and C plus B and D. As can be seen from the circuit, if a 0 or down voltage is applied to input A and a 0 is applied to input C, or if a 0 is applied to input B and a 0 is applied to input D, the output has a 1 or an up voltage. In all other combinations of 0's and 1's at the inputs A, B, C and D, the output is a 0 or down voltage.

The CMOS OAI circuit is shown in structured topological form in Fig. 2 wherein a silicon dioxide layer 10 is formed on a silicon substrate 12 with a voltage supply metal strip 14, a metal strap 16 and a ground metal strip 18 being disposed on silicon dioxide layer 10. Each of the P channel transistors is formed in a conventional manner under voltage supply metal strip 14, and each of the N channel transistors is formed in a conventional manner under ground metal strip
18. Contacts 20 are connected to appropriate diffusion regions in silicon substrate 12, as indicated in Fig. 2. Metal strap 16 interconnects the P channel and N channel transistors at the output terminal.

It should be understood that this OAI circuit may be expanded in the AND direction by adding another row of N channel transistors and another column of...