Browse Prior Art Database

Inverted Carry Propagation Chain

IP.com Disclosure Number: IPCOM000050068D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR [+2]

Abstract

This article describes a ripple arithmetic logic unit (RALU) in which the intra stage carry signal propagation time is reduced and the intra stage carry signal degradation is eliminated.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Inverted Carry Propagation Chain

This article describes a ripple arithmetic logic unit (RALU) in which the intra stage carry signal propagation time is reduced and the intra stage carry signal degradation is eliminated.

An n-bit RALU consists of a serially connected chain of a number n of individual stages, numbered from 0 to n-1. Each stage takes three inputs, A(i), B(i), and Carry Cin(i), and generates two outputs, carry (C) out and R(1). The results of such an arithmetic logic unit are not complete until the final stage, stage n-1, has received its correct inputs and generated its output. Under worst case conditions, the carry signal input to the last stage is a result of the carry signal propagating through n-1 stages.

Each stage requires X amount of time, called the intra stage carry propagation time, to propagate its carry signal from the Input node A to the output node B. As the index of each stage increases, the drive of its carry signal decreases. In order to decrease this, the intra stage carry propagation time must be reduced and the accumulative effect of the intra stage carry signal degradation must also be reduced. The inverted carry propagation chain (ICPC) of the present invention achieves these desirable results and is characterized by each stage having a single inverter comprised of transistors 10 and 11 which are used to invert the carry signal inputted at node A and drive it through a pass transistor 12 to node B where it can be inputted to any succeeding stage and decrease the time for the carry signal to change from its preset value.

By combining these features the accumulative effect of the inter stage carry signal degra...