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Output Latch Up Protection for CMOS Drivers

IP.com Disclosure Number: IPCOM000050071D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+2]

Abstract

Latch up of a driver circuit which may be triggered by noise on its output terminal is prevented by inserting a diode between the output terminal and the P channel transistor in complementary metal oxide semiconductor (CMOS) technology.

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Output Latch Up Protection for CMOS Drivers

Latch up of a driver circuit which may be triggered by noise on its output terminal is prevented by inserting a diode between the output terminal and the P channel transistor in complementary metal oxide semiconductor (CMOS) technology.

In the CMOS driver circuit illustrated in Fig. 1, without the diode D, the voltage at the output terminal can at times exceed the supply voltage VH, due, e.g., to transmission line reflection or noise coupling into the load capacitor CL, and cause an undesirable latch up. When such a high voltage appears at the output terminal, the P+ drain of the P channel transistor acts as an emitter of a parasitic vertical PNP transistor since the N-well N1, as indicated in Fig. 2, is held at the supply voltage VH, causing the latch-up of the driver circuit.

By adding the diode D between the P channel and N channel transistors, as indicated particularly in N-well N2 in Fig. 2, when the voltage is low at the input terminal, the voltage at the output terminal becomes VH'=VH-Vfb, where Vfb is the forward voltage drop across the diode D. If a noise voltage coupled to the output terminal raises its potential above the voltage VH', this high voltage causes diode D to become reverse biased rather than to forward bias the emitter base junction of the parasitic PNP transistor. The schematic layout of the circuit of Fig. 1 is illustrated in Fig. 2 with N-wells Nl end N2 formed in a P type substrate, with the N...