Browse Prior Art Database

Associative Comparator

IP.com Disclosure Number: IPCOM000050098D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Hanna, CA: AUTHOR

Abstract

The construction of a plurality of random access memories (RAMs) on a single chip enables simultaneous comparison of a binary value with a plurality of limits. The RAMs are arranged to compare either single or double length words, and control circuits permit the recovery of matched values after comparison.

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Associative Comparator

The construction of a plurality of random access memories (RAMs) on a single chip enables simultaneous comparison of a binary value with a plurality of limits. The RAMs are arranged to compare either single or double length words, and control circuits permit the recovery of matched values after comparison.

Referring to Fig. 1, the comparator comprises a pair of identical channels 0 and 1 with only channel 0 shown schematically. Each channel has a pair of RAMs 3, 4 into which are each loaded a plurality of 16-bit lower limit values from buses 5, 6, and RAMs 7, 8 are each loaded with a plurality of 16-bit upper limit values. Input data words of 16 bits are then applied along buses 9, 10 and compared successively with the stored values in each RAM at comparator circuit 11 for the respective RAM. Comparison occurs simultaneously at all RAMs but successively for stored values therein. Parity checking is done by circuits 12.

The results of each comparison are supplied to control circuit 13 which provides an output signal for each match at terminal 14. Control circuit 13 in each channel is enabled for inside or outside limit comparison by input signals from RAMs 3, 4. Control circuit 13 also forces a match to be indicated for the limits in RAMs 3, 7 when disabled by an input signal at terminal 15, and forces a match to be indicated for the limits in RAMs 4, 8 when disabled by an input signal at terminal 16. It will be noted that the 32 bit input word can be compared by combining RAMs 3 and 4 for storing a 32-bit lower limit and combining RAMs 7 and 8 for...