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Using a Doubly Implanted Polysilicon Layer for Forming Base and Emitter Regions

IP.com Disclosure Number: IPCOM000050107D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

In the prior art, bipolar transistors have been described wherein doped polysilicon is used simultaneously as a source of diffusion for forming extrinsic base regions and for linking the base to the base metallization. In the fabrication of these bipolar transistors, the intrinsic base and emitter regions are typically formed subsequent to the formation of the extrinsic base regions.

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Using a Doubly Implanted Polysilicon Layer for Forming Base and Emitter Regions

In the prior art, bipolar transistors have been described wherein doped polysilicon is used simultaneously as a source of diffusion for forming extrinsic base regions and for linking the base to the base metallization. In the fabrication of these bipolar transistors, the intrinsic base and emitter regions are typically formed subsequent to the formation of the extrinsic base regions.

It has been found advantageous to employ ion implantation, rather than conventional diffusion, to form the intrinsic base and emitter regions. This is especially so when very shallow emitter and intrinsic base junction depths are to be realized. As described here, it is preferable to first form a layer of polysilicon in intimate contact with the silicon where emitter and intrinsic base regions are to be formed. The layer of polysilicon is then implanted with p-type and n-type impurity ions, the typical impurities being boron and arsenic, respectively. The silicon wafer is then subjected to suitable heat cycling to drive the impurities into the monocrystalline silicon to desired junction depths. By applying this process, bipolar transistors of both NPN and PNP types, as shown in Figs. 1A through 2C, may be fabricated simultaneously on the same wafer.

Fig. 1A shows a top view of the doubly implanted polysilicon layer 1 on the semiconductor structure. Fig. 1B shows a cross sectional view taken along line 1B-1B in Fig. 1A, while Fig. 1C shows a cross sectional view taken along line 1C- 1C in Fig. 1A. As shown in Figs. 1B and 1C, the thin doubly implanted layer of polysilicon produces a shallow N/+/- type emitter region 3 in response to heat cycling drive-in. Subsequen...