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Single Step Process for Forming Isolation Trenches of Different Depths in a Silicon Substrate

IP.com Disclosure Number: IPCOM000050108D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+4]

Abstract

Many semiconductor device structures require dielectric isolations in trenches of different depths. It is advantageous to form the isolation regions in a single process step.

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Single Step Process for Forming Isolation Trenches of Different Depths in a Silicon Substrate

Many semiconductor device structures require dielectric isolations in trenches of different depths. It is advantageous to form the isolation regions in a single process step.

Fig. 1 shows trenches 10, 12 of different depths formed in a silicon substrate
14. The trenches 10, 12 are formed in the substrate by conventional RIE (reactive ion etching) techniques. The shallow trench 10 is coated with a thin oxidation inhibiting layer 16, such as silicon nitride. The silicon nitride layer 16 can be formed either by low pressure chemical vapor deposition or by N ion implant into the shallow trench 10. A blockout mask (not shown) is placed over the deep trench 12 during the nitride formation. The nitride deposit or implant is subsequently heat treated to convert the implanted or deposited region into a thin silicon nitride Si(3)N(4) layer 16.

Layer 24 is a thicker (approximately 500 Angstoms) nitride layer to prevent the oxidation of the top silicon surface while the trenches are being oxidized.

In Fig. 2, the deep trench 12 is filled with silicon dioxide 18 in a conventional thermal oxidation process. The layer 16 prevents oxidation in the shallow trench
10. The layer 16 is formed to a thickness to inhibit the oxidation of the trench 10 until the deeper trench 12 is partially filled with silicon dioxide, such that at the completion of the oxidation, a planar surface 20 is formed...