Browse Prior Art Database

Process to Improve Reliability and Performance of Double Polysilicon Gate Device

IP.com Disclosure Number: IPCOM000050127D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Aboelfotoh, MO: AUTHOR [+2]

Abstract

In a process for making an FET device having two polysilicon gates, the first polysilicon layer 20 is deposited following first gate 16 enhancement or depletion implant to form an N-channel 14 in a P-type substrate 10, as shown in Fig. 1. A layer of silicon dioxide 22 is then deposited over the first polysilicon layer, and is followed by the patterning of the first polysilicon layer using a dry etching technique such as reactive ion etching. The second gate oxide layer 18 is then regrown after the removal of the first gate oxide layer. The interpoly oxide layer 24 (the silicon dioxide layer between the first and second polysilicon layers 20 and 26) is normally grown at the same time as the second gate oxide layer 18.

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Process to Improve Reliability and Performance of Double Polysilicon Gate Device

In a process for making an FET device having two polysilicon gates, the first polysilicon layer 20 is deposited following first gate 16 enhancement or depletion implant to form an N-channel 14 in a P-type substrate 10, as shown in Fig. 1. A layer of silicon dioxide 22 is then deposited over the first polysilicon layer, and is followed by the patterning of the first polysilicon layer using a dry etching technique such as reactive ion etching. The second gate oxide layer 18 is then regrown after the removal of the first gate oxide layer. The interpoly oxide layer 24 (the silicon dioxide layer between the first and second polysilicon layers 20 and 26) is normally grown at the same time as the second gate oxide layer 18. This is followed by the deposition and patterning of the second polysilicon layer 26 to form a double polysilicon gate device, this device being isolated from other devices of the integrated circuit chip by field oxide 12, as shown in Fig. 1.

It is found that the first polysilicon edge can be lifted after interpoly oxidation, as shown in Fig. 1, thus seriously affecting the reliability and performance of the device. This problem is eliminated by the present process which will be understood by also referring to Figs. 2 and 3.

In Fig. 2, the interpoly oxide layer 24 is grown prior to the removal of the first gate oxide layer 14. The interpoly oxidation cycle is adjusted so...