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Serial Data Link Support of Multiple Frequency Devices Using Frequency Discrimination

IP.com Disclosure Number: IPCOM000050132D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

McDowell, AW: AUTHOR [+2]

Abstract

Over the useful life of a product, technology usually advances to the point where higher performance devices could be designed and attached via a serial link which would enhance the product's capability and/or performance. A serial link designed to operate with devices at various, selectable, high speed data rates can take advantage of these technology advances as they occur, even though the specific frequencies that will be required in the future are not known at the time of the initial link design. This can be accomplished using a frequency discrimination technique as described below.

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Serial Data Link Support of Multiple Frequency Devices Using Frequency Discrimination

Over the useful life of a product, technology usually advances to the point where higher performance devices could be designed and attached via a serial link which would enhance the product's capability and/or performance. A serial link designed to operate with devices at various, selectable, high speed data rates can take advantage of these technology advances as they occur, even though the specific frequencies that will be required in the future are not known at the time of the initial link design. This can be accomplished using a frequency discrimination technique as described below.

Shown in Fig. 1 is a means to attach secondary devices 10, 12, capable of operating at various serial data rates, to a single serial data link 14 but allow each device to operate at its maximum data rate. A Frequency Discriminator (FD) F1, F2 in each secondary device constantly examines the clock being transmitted from a multi frequency generator (MFG) in primary device 18 and determines whether it is less than or equal to a reference clock REF1, REF2 in the secondary device. If so, the clock signal is passed to the Data Link Control (DLC) logic in the secondary device to allow examination of the serial data on line 20 by the Device Logic (DL). If the clock transmitted from the primary device is greater than the reference clock, the FD does not pass the clock to the secondary DLC.

The primary device 18 initially polls all valid addresses at a frequency that will be accepted by all secondary devices to determine which devices are attached. It can then change the serial link's data rate to the maximum rate that a particular device can handle in order to transmit or receive blocks of data from that secondary.

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