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Browse Prior Art Database

Structured Macro

IP.com Disclosure Number: IPCOM000050153D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Stoops, EH: AUTHOR

Abstract

Existing integrated circuit chip images typically have three vertical power bus pairs located on the left and right sides and up the middle of the chip. One problem with this chip image is that horizontal wiring channels are readily blocked after the placement of a logic macro on the chip.

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Structured Macro

Existing integrated circuit chip images typically have three vertical power bus pairs located on the left and right sides and up the middle of the chip. One problem with this chip image is that horizontal wiring channels are readily blocked after the placement of a logic macro on the chip.

One approach to improving the wirability of an integrated circuit chip which employs large logic circuit macros and design automation principles is to increase the number of vertical power bus clusters. The principle of the invention disclosed here is to require that every macro which is located adjacent to a power bus cluster have its opposite side separated from the next available power bus cluster by a predetermined free area to maintain wirability to macros which will be placed adjacent to the existing macro.

Referring to Fig. 1, the chip image 1 is divided into six vertical columns 2 with a vertical power bus 3 bounding the leftmost and rightmost edges of the chip and five vertical power bus clusters 4 separating the respective six columns 2.

Each column 2 is 18 macro cells wide, and each vertical power bus cluster 4 is two macro cells wide. Each macro cell can contain up to 10 wiring channels.

A macro 5 (Fig. 2) can have a width of eight cells, 16 cells, 28 cells, 36 cells, 48 cells, 56 cells, and so on, and in each case has its left end start at the right side of a first vertical bus cluster 3 or 4 and its right side terminate at a position so as to leave a width of two macro cells before the left side of the next power bus begins. This insures that sufficient free wiring channels 6 are available after the chip has been partitioned into the areas for macro placement, in...