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# Most Significant Bit Detector with Predicted Parity

IP.com Disclosure Number: IPCOM000050160D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 53K

IBM

## Related People

Rackl, WK: AUTHOR [+2]

## Abstract

To facilitate hardware checking of logic, a parity predict is included in a most significant bit detector.

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Most Significant Bit Detector with Predicted Parity

To facilitate hardware checking of logic, a parity predict is included in a most significant bit detector.

Fig. 1 is a block diagram of the most significant bit detector with an independent parity predict. From the 32-bit input word A (A0, ..., A31, high to low order), a 6-bit number B (B0, ..., B5, high to low order) is generated representing the bit location of the most significant 1. The odd parity of B, BP is generated independently of B from the same primary inputs A0, ..., A31. However, generating the complement outputs B0, ..., B5, BP was found to be more efficient in actual implementation. Fig. 2 generates the equations for B0,..., B5. Two points should be noted:
1. The redundancy inherent in the expressions can be eliminated or

retained to permit sharing, depending on which course yields

the best overall efficiency. For example, the expression

for B4 includes the irredundant factor A(2)/3/ which could be

replaced by A(0)/3/ containing the redundant portion A(0)/1/.

The factor A(0)/3/ will actually be used since it can be shared

with terms needed for the other expressions. On the other

hand, the irredundant term A(1) of the expression for B5 will

be used instead of A(0)/1/ because no sharing is done.
2. B5 is expressed in terms of 4-bit groups, so that joint 4-bit

groups for expressions B4 and B5 could be implemented as a

common set of repeated macros. Fig. 3 shows the 4-bit group

macro.

Fig. 4 shows the...