Browse Prior Art Database

Dynamic Storage Cleanup

IP.com Disclosure Number: IPCOM000050171D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Kindseth, DM: AUTHOR

Abstract

Dynamic storages are subject to intermittent bit failures which can become uncorrectable by the error correcting circuitry (ECC) if a cleanup operation is not periodically performed. Normally, the cleanup operation is a separate operation, and if done through programming, there is performance degradation. Dynamic storages also require periodic refresh. Normally, during refresh the data is not read out and applied to the error correcting circuitry. The present arrangement provides the ability to do error correction and a store operation during refresh.

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Dynamic Storage Cleanup

Dynamic storages are subject to intermittent bit failures which can become uncorrectable by the error correcting circuitry (ECC) if a cleanup operation is not periodically performed. Normally, the cleanup operation is a separate operation, and if done through programming, there is performance degradation. Dynamic storages also require periodic refresh. Normally, during refresh the data is not read out and applied to the error correcting circuitry. The present arrangement provides the ability to do error correction and a store operation during refresh.

A typical main storage address control circuit is shown in Fig. 1 where addressing is in the normal mode when latch 60 is reset and in the refresh mode when latch 60 is set. Latch 60 is set only when AND circuit 55 has determined that free-running refresh period counter 50 is in the "all ones" state. The set output of refresh latch 60 increments refresh counter 30 which addresses dynamic storage 10 via AND circuit 35 and OR circuit 25. AND circuit 35 is conditioned only when latch 60 is in the set state. During normal operation the address in address register 15 addresses storage with a bit line select 16 and word line select via AND circuit 20 and OR circuit 25. AND circuit 20 is conditioned by the reset output of latch 60.

During a normal storage fetch operation, data read from storage 10 is passed through the error correcting logic 70 prior to entering data register 75 (Fig. 2). When error correcting logic 70 detects a correctable error, it provides a signal over line 71 to provide an input to AND circuit 57. In this instance, AND circuit 57 is conditioned only when refresh latch 60 is set. The output of AND circuit 57 is used to force a refresh with write back of corrected data. The address at which the corrected data is written back is furnished via counters 30 and 32. Counter 30 provides the refresh word address, and counter 32 provides the data word select address for both the fetch and write back of corrected data operations. The output of refresh counter 30 conditions AND circuit 35, as in Fig. 1, and when the output of counter 30 is all ones as detected by AND circuit 31, bit counter 32 is incremented. The output of bit counter 32 is applied to AND circuit 36 which is conditioned by the set output of latch 60. AND circuit 36 provides a bit line select signal via OR circuit 26 to storage 10. During normal operation, the bit line select signal from storage address register 15 is passed via AND circuit 21 and OR circuit 26 where AND circuit 21 is conditioned by the...