Browse Prior Art Database

Variable Priority Memory Refresh

IP.com Disclosure Number: IPCOM000050172D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Beacom, TJ: AUTHOR [+2]

Abstract

In order to enhance computer system performance where the computer system includes a dynamic storage requiring refresh, fetch and store operations have priority over refresh operations until two refresh operations have been requested. When one refresh request is pending, a refresh operation is performed if no request for a fetch or store is pending. However, when one refresh request is pending and another refresh request occurs, the refresh operation is given higher priority than a fetch or store operation. After one of the two pending refresh operations is performed, priority reverts to a fetch or store operation. Thus refresh operations are delayed by only the time between refresh requests, and yet fetch and store operations have highest priority most of the time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Variable Priority Memory Refresh

In order to enhance computer system performance where the computer system includes a dynamic storage requiring refresh, fetch and store operations have priority over refresh operations until two refresh operations have been requested. When one refresh request is pending, a refresh operation is performed if no request for a fetch or store is pending. However, when one refresh request is pending and another refresh request occurs, the refresh operation is given higher priority than a fetch or store operation. After one of the two pending refresh operations is performed, priority reverts to a fetch or store operation. Thus refresh operations are delayed by only the time between refresh requests, and yet fetch and store operations have highest priority most of the time.

In state 1 of the state diagram (Fig. 1), no refresh requests are pending. In state 2, one refresh request is pending, but fetch and store requests have higher priority. A refresh occurs only if no fetch or store operation has been requested. In state 3, two refresh requests are pending; thus the next storage operation will be a refresh operation.

The refresh control circuitry (Fig. 2) includes a refresh request latch 11 having an L1 portion which takes the value of the data input when C clock 18 occurs and an L2 portion which is set to the value of the L1 portion when B clock 19 occurs. The C and B clocks are free running and do not overlap. The refresh control circuitry also includes refresh demand latch 13 which also receives the C and B clocks 18 and 19, respectively. In state 1, latches 11 and 13 are in a state where the outputs thereof, 12 and 14, respectively, are in the zero state. Thus, there is no output from OR circuit 16 to provide a Do Refresh Next signal 17.

A Refresh Request pulse 3 is applied to refresh request latch 11 via OR circuit 6 to place the control circuit in st...