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Priming Cache Memories for Rapid Data Transfers

IP.com Disclosure Number: IPCOM000050193D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Reed, DG: AUTHOR [+2]

Abstract

A peripheral system includes a direct-access storage device (DASD) having a cache for enhancing performance. In transferring data signals from DASD to cache, it is desired to transfer a predetermined number of such data signals. For facilitating the transfer, a plurality of system storage address registers (SSAR) are provided. Immediately preceding the transfer, the SSARs are all loaded with addresses pointing to cache registers which are to receive a sequence of data blocks on DASD. The transfer is then initiated with no interruption such that a high-speed set of signals is rapidly transferred from DASD to cache at diverse address locations in rapid succession.

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Priming Cache Memories for Rapid Data Transfers

A peripheral system includes a direct-access storage device (DASD) having a cache for enhancing performance. In transferring data signals from DASD to cache, it is desired to transfer a predetermined number of such data signals. For facilitating the transfer, a plurality of system storage address registers (SSAR) are provided. Immediately preceding the transfer, the SSARs are all loaded with addresses pointing to cache registers which are to receive a sequence of data blocks on DASD. The transfer is then initiated with no interruption such that a high-speed set of signals is rapidly transferred from DASD to cache at diverse address locations in rapid succession.

One or more hosts access data on DASD at any track T through a control, such as a control unit. The host can access the data via a cache in subsystem storage (SS). Along with the cache, SS includes a directory pointing to the data in the cache based on the address of the data originally in DASD. Various replacement and data prefetching algorithms are employed to ensure that the cache contains data most wanted by the host. The control includes a portion for directly access channel commands are often referred to as channel command words (CCWs) which are chained together in a series of operations.

The internal operations of transferring data between DASD and cache are based upon the chaining principle of CCWs through a chain of internal command words (ICWs). To...