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Browse Prior Art Database

CMOS Decoder Circuit

IP.com Disclosure Number: IPCOM000050219D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

This publication relates to improvements in CMOS (complementary metal oxide semiconductor) decoder circuits, and particularly to a decoder circuit which does not dissipate DC power. Fig. 1 shows a known CMOS decoder circuit and associated waveform.

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CMOS Decoder Circuit

This publication relates to improvements in CMOS (complementary metal oxide semiconductor) decoder circuits, and particularly to a decoder circuit which does not dissipate DC power. Fig. 1 shows a known CMOS decoder circuit and associated waveform.

A drawback of the circuit of Fig. 1 is that when a decoder is selected, no power is dissipated since the A(1)/A(1) ... A(n)/A(n) inputs will be low, but the unselected decoders all dissipate power, since both the load device and at least one input device will be on. A circuit (and associated waveforms) which overcomes this is shown in Fig. 2.

In the operation of the circuit of Fig. 2, during precharge, node 1 is precharged high with only AC current and node 2 follows through the 0(2) device. Word lines A and B are clamped to ground. When precharge ends, 0(1) and 0(2) rise to + V(DD) and the address lines conditionally rise to V(DD), conditionally discharging node 1 but not node 2 and no DC current flows. 0(1) rises, causing node 2 to become the inverse of node 1 (low selected, high unselected). 0(R1) or 0(R2) comes up to select the word line.

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