Browse Prior Art Database

Reduction of Branch Delay by out of Sequence Decoding Under Control of a Decode History Table

IP.com Disclosure Number: IPCOM000050222D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+2]

Abstract

A decode history table containing branch taken indicators provides an alert to an instruction decoder to signal an upcoming branch instruction. The alert signal causes the instruction decoder to decode the branch instruction out of sequence, one cycle early. The subsequent cycle is then used to decode the instruction preceding the branch.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Reduction of Branch Delay by out of Sequence Decoding Under Control of a Decode History Table

A decode history table containing branch taken indicators provides an alert to an instruction decoder to signal an upcoming branch instruction. The alert signal causes the instruction decoder to decode the branch instruction out of sequence, one cycle early. The subsequent cycle is then used to decode the instruction preceding the branch.

For a processor with a one-cycle cache, the cycle delay inherent in a taken branch is eliminated through the out of sequence decoding of the branch instruction. If the branch is correctly predicted, the delay in decoding the preceding instruction does not impact performance. To assure executionsequence the branch must be executed in parallel with the preceding instruction. This requirement can be relaxed for machines with a two-cycle cache access.

The decode history table will utilize the length code of the preceding instruction so that the recurrence of the instruction pattern will trigger the branch decode on the instruction cycle reserved for the preceding instruction.

1