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Improving the Performance of a Transfer Gate PLA Structure

IP.com Disclosure Number: IPCOM000050260D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

Present PLA (programmable logic array) implementations require a shared diffusion contact hole within each basic cell. These contacts limit the ultimate density of this type of structure. Described is a logic structure in which no contact holes are required within the basic cell.

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Improving the Performance of a Transfer Gate PLA Structure

Present PLA (programmable logic array) implementations require a shared diffusion contact hole within each basic cell. These contacts limit the ultimate density of this type of structure. Described is a logic structure in which no contact holes are required within the basic cell.

Fig. 1 is a circuit schematic showing FET devices T1 and T2 which charge and discharge, respectively, the logic terms P1 and P2. Logic term P1 consists of devices T3 through T6A, and logic term P2 consists of devices T7 through T10A. Each product term is personalized with depletion masks shown as cross-hatched gates in Fig. 1. Although a specific personality is illustrated, all variations are allowed. Devices T11 and T12 function as an inverting amplifier.

By repeating the schematic in Fig. 1, a vertical column of product terms can be generated to form a logic array. The OR array is fabricated in like fashion.

Lines I1 through I5 are the logic inputs which may be paired to form true and complement data lines. Inputs I4 and I5 are special in that they can be used to select which product term (either P1 or P2) will be activated. In other words, they act as multiplexers which provide for the sharing of charge and discharge circuits and amplifiers.

Although only two product terms per amplifier are illustrated, it should be understood that more than two can be multiplexed, if desired.

A transfer gate structure has delay characteristic...