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Browse Prior Art Database

Refresh Algorithm

IP.com Disclosure Number: IPCOM000050261D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+3]

Abstract

An algorithm is described that reduces the wait time of central processing unit (CPU) storage requests, thereby increasing CPU performance. Dynamic memory is refreshed during a known period when no CPU storage requests have occurred rather than allowing the refresh requests and CPU requests to occur asynchronously.

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Refresh Algorithm

An algorithm is described that reduces the wait time of central processing unit (CPU) storage requests, thereby increasing CPU performance. Dynamic memory is refreshed during a known period when no CPU storage requests have occurred rather than allowing the refresh requests and CPU requests to occur asynchronously.

Storage priorities are assumed to be as shown in the table below. CPU and cycle steal requests normally have priority over low priority refresh. Processor Storage Priorities: 1. High Priority Refresh.
2. CPU Transfer. 3. Cycle Steal Transfer. 4. Low Priority Refresh.

Dynamic memories need to continually refresh a subset of all memory locations within a specific time interval. These memory refresh cycles can cause CPU storage cycles to be held pending, thus degrading CPU performance. The method described here detects a period of inactive processor storage requests so that a refresh cycle can be generated. The result is that performance (based on typical instruction mixes) is reduced due to refresh by only a fraction of 1%. Without this mechanism, refresh can cause reduction of approximately 8 to 10% in processor performance.

The refresh cycle for a representative processor is assumed to be 10.8 microseconds. During this interval a low priority request for a storage cycle (to refresh) is initiated at the start of the last 3 microcycles of I-phase (instruction fetch portion of each execution). These 3 microcycles define, at least, a peri...