Browse Prior Art Database

Circuit to Increase Read Access Time for a Microprocessor

IP.com Disclosure Number: IPCOM000050262D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Davis, TH: AUTHOR [+2]

Abstract

In order to utilize slower, and hence less costly, memory and input/ output (I/O) devices with a microprocessor, it is necessary to provide a longer read access signal. For instance, in the Intel 8085A microprocessor, read data is gated onto the bus by the RD signal from the microprocessor. This signal has a duration of approximately 400 ns, and the microprocessor is operated with a 320 ns clock cycle time. When data set-up time is taken into account, the read access time when gated by the RD signal is actually only 280 ns. With this access time it is normally necessary to use a high speed memory with the system.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 2

Circuit to Increase Read Access Time for a Microprocessor

In order to utilize slower, and hence less costly, memory and input/ output (I/O) devices with a microprocessor, it is necessary to provide a longer read access signal. For instance, in the Intel 8085A microprocessor, read data is gated onto the bus by the RD signal from the microprocessor. This signal has a duration of approximately 400 ns, and the microprocessor is operated with a 320 ns clock cycle time. When data set-up time is taken into account, the read access time when gated by the RD signal is actually only 280 ns. With this access time it is normally necessary to use a high speed memory with the system.

The circuit shown in Fig. 1 is utilized to detect an early read cycle from the 8085A microprocessor 8 by monitoring the status lines So S1 and IO/M.

Referring to the timing diagrams shown in Fig. 2, the circuit of Fig. 1 operates by latch 10 detecting the ALE signal from microprocessor 8 and by latch 12 synchronizing the detected ALE signal with the system clock CLK signal. NAND gate 14 detects the early read operation by monitoring the SO,S1 and IO/M signals. The S1 signal and the outputs of gate 14 and latch 12 are provided to NAND gate 16 which, in turn, provides the early read signal to OR gate 18. It should be noted that OR gate 18 can provide either the initial RD signal from the microprocessor 8 or the early read signal from gate 16.

It should be noted that this circuit is compatible with b...