Browse Prior Art Database

Channel Check System

IP.com Disclosure Number: IPCOM000050264D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Eggebrecht, LC: AUTHOR [+2]

Abstract

Utilization of a single interface line channel check system with fault location capabilities reduces the number of lines and complexity of a system channel error and notification system. It further allows for the notification of an error condition upon attempted use of the resource and provides information about the location of the error component to a diagnostic or operating system.

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Channel Check System

Utilization of a single interface line channel check system with fault location capabilities reduces the number of lines and complexity of a system channel error and notification system. It further allows for the notification of an error condition upon attempted use of the resource and provides information about the location of the error component to a diagnostic or operating system.

Fig. 1 illustrates the hardware implementation of the single line channel check system, and Fig. 2 shows timing diagrams useful in understanding the operation of Fig. 1. When a channel attached device, suchas a memory card or an input/output adapter, detects its set of memoryand/or input/output addresses, it activates the channel check line if there is an error condition detected or pending in the device. The line must be activated within that portion of the bus cycle where the input/ output or memory address is valid on the system bus. Parity errors are easily generated within the bus cycle and thus can be activated within the bus cycle. Other error conditions are latched within the attachments and are then used to activate the channel check line when the processor attempts to address the device. All devices are "dot ORed" on the channel check line which, when activated, sets a latch at the processor end of the channel. This latch setting causes an interrupt signal to be provided to the processor and clocks the bus address and status into the check address regis...