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Browse Prior Art Database

Method of Forming Polysilicon Filled Isolation Regions in an Integrated Circuit Device

IP.com Disclosure Number: IPCOM000050297D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

Isolation regions made by this process have minimal stress, which otherwise may produce leakage.

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Method of Forming Polysilicon Filled Isolation Regions in an Integrated Circuit Device

Isolation regions made by this process have minimal stress, which otherwise may produce leakage.

The starting substrate is a P type wafer 10 provided with an N type epitaxial layer 12, and an N+ region 14, useful as a sub-collector. Obviously, the impurity types could be reversed. Surface SiO(2) layer 16 is formed by oxidizing the surface of layer 12, an overlying Si(3)N(4) layer 18 deposited by chemical vapor deposition techniques on layer 16, and a relatively thick layer 20 of chemically vapor deposited oxide deposited on layer 18. A resist layer 22 is deposited on the surface which is exposed and developed to form opening 24 overlying the desired isolation regions.

The exposed regions of layers 18 and 20 are removed by reactive ion etching, and resist layer 22 is stripped and deep trenches 26 are formed by further reactive ion etching, as indicated in Fig. 2. The substrate is then thermally oxidized and a thin chemically vapor deposited layer of oxide 28 deposited, as indicated in Fig. 2. A short exposure to reactive ion etching removes the portion of layer 28 in the bottom surface 30 of trench 26 and the upper surface of layer 20.

A relatively thick layer of polysilicon material is deposited on the surface of the substrate by chemical vapor deposition techniques to a depth sufficient to fill the trench 26. The surface polysilicon is removed by planarizing techniques and the masking layers 20, 16 and 18 are removed by reactive ion etching techniques, which result in the device having the cross section shown in Fig. 3. The remaining polysilicon region 32 has a top surface in the same plane as the top surface of layer 12. During the mask...