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Enhancement to Chip Test by Isolation

IP.com Disclosure Number: IPCOM000050306D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 15K

Publishing Venue

IBM

Related People

Rosales, BC: AUTHOR

Abstract

"Chip Test by Isolation" requires that tests which measure chip output pads be independent from tests with measures for Shift Register Latches (SRLs) on the chip. This article removes this independence requirement, thereby providing support for the traditional Level Sensitive Scan Design (LSSD) test sequences (1,2). Features 1. Makes use of LSSD design constraints and Chip Test by Isolation circuitry while requiring a small amount of additional circuitry and wiring at the chip level. 2. Reduces test data volume and tester time required by the "Chip Test by Isolation" technique. Description

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Enhancement to Chip Test by Isolation

"Chip Test by Isolation" requires that tests which measure chip output pads be independent from tests with measures for Shift Register Latches (SRLs) on the chip. This article removes this independence requirement, thereby providing support for the traditional Level Sensitive Scan Design (LSSD) test sequences (1,2). Features
1. Makes use of LSSD design constraints and Chip Test by

Isolation circuitry while requiring a small amount of

additional circuitry and wiring at the chip level.
2. Reduces test data volume and tester time required by the

"Chip Test by Isolation" technique.

Description

Chip Test by Isolation (2) requires the separation of output measures and SRL measures because chip SRL states are altered by the output measurement process described herein, and because chip output states are altered by the chip SRL measurement process described therein. By adding a small amount of additional hardware, it is possible to describe a process in which the measurement of the chip output states does not alter the chip SRL states. The basic idea is to capture the states of the outputs of the chip under test (CUT), which do not directly drive package outputs, into the L1's of the SRL's off the CUT, but to delay the measurement of them until the states of the SRL's on the CUT are measured. That is, a single package scan-out will be able to measure both the pending CUT primary output (PO) states and the CUT SRL states. This means that there is no need to generate independent tests which measure only PO's or only SRL's, but rather, the traditional LSSD tests, which allow these measurements to be combined in the same test sequence (Fig. 1) can be handled. This will reduce (1) the required number of test sequences, (2) the number of package scan-ins and scan-outs, and (3) the time to apply the tests at the tester.

The hardware that must be added is minimal. Gate the A and B clocks on each chip with the INHIBIT of the Chip Test by Isolation (2) such that: (1) when the INHIBIT is "on", then the A and B clocks are forced "off" (this is already required for the system clocks by (2); and (2) when the INHIBIT is "off" and all clocks are inactive, then the B clocks can control the L2 latches (the INHIBIT is the only B clock gating allowed). This gating will allow the SRL's off the CUT to retain the captured PO states in their L1 latches while preserving the scanned-in states in their L2 latches.

The test sequence of Fig. 1 assumes that the SRL values to be measured are in the L2 latches of the SRL's before the SCAN-OUT. The steps given in Fig. 2 also assume that the SRL values to be measured are in the L2 latches before the SCAN-OUT. However, many times the SRL values are first captured in the Ll latches and are then moved to the L2 latches by establishing the stability state and then applying the B clocks. Under these conditions, a shorter sequence of steps can be given (Fig. 3). The steps in Fig. 2 are gener...