Browse Prior Art Database

Chip Partitioning Aid

IP.com Disclosure Number: IPCOM000050307D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Graf, MC: AUTHOR [+2]

Abstract

Generation of test data for logic assemblies containing many thousands of gates is an extremely expensive, time consuming task. If the assembly is sufficiently large, it may even exceed the size limitations of available test pattern generation programs.

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Chip Partitioning Aid

Generation of test data for logic assemblies containing many thousands of gates is an extremely expensive, time consuming task. If the assembly is sufficiently large, it may even exceed the size limitations of available test pattern generation programs.

These problems have been addressed by using programs to partition the logic into independent subsets. A design strategy using Level Sensitive Scan Design (LSSD)(*) is assumed. In this case, each LSSD latch becomes a candidate both for a point of control for test data application, and for a point of observation for test results.

Unfortunately, in practical logic structures, this does not provide for clean divisions into easily manageable pieces (partitions) for test pattern generation. First, there is frequently at least one partition that contains a significant portion of the logic assembly, which may in itself be near or above the practical test pattern generation limits. Second, the partitions may not be made completely independent, to minimize the size of each individual partition. This means that the same logic may appear in several partitions, requiring that the test pattern generation programs work on this logic several times.

The problems of partition overlap and partition size can essentially be eliminated by incorporation of special circuitry on each chip in a logic assembly. Placement of an LSSD latch in series with each chip data output, as illustrated, guarantees that the maximum...