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High Voltage Power Schottky Barrier Diodes

IP.com Disclosure Number: IPCOM000050313D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

This is a proposal for the fabrication of an improved high-voltage Schottky barrier diode (SBD) with superior electrical characteristics. Through suitable adaptation of deep dielectric isolation techniques, a maximized reverse breakdown voltage is achieved without adversely impacting the forward voltage characteristic. These Power SBDs allow handling of currents in the range of 10 to 100 A, and withstand reverse voltages of about 20 to 75 V. Fig. 1 conceptually depicts the proposed general SBD structure.

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High Voltage Power Schottky Barrier Diodes

This is a proposal for the fabrication of an improved high-voltage Schottky barrier diode (SBD) with superior electrical characteristics. Through suitable adaptation of deep dielectric isolation techniques, a maximized reverse breakdown voltage is achieved without adversely impacting the forward voltage characteristic. These Power SBDs allow handling of currents in the range of 10 to 100 A, and withstand reverse voltages of about 20 to 75 V. Fig. 1 conceptually depicts the proposed general SBD structure.

A broad outline of a preferred process sequence which will practically realize the basic structure of Fig. 1 is described as follows: 1. With reference to Fig. 2, starting with an N+ silicon

substrate 2, grow on it about 4 Mum thick N- epitaxial

silicon layer 4 of about 0.5-5 ohm-cm resistivity.

2. Form about 1 Mum thick silicon dioxide (SiO(2)) 6 at the

silicon surface.

3. Using photolithography, etch annular windows in SiO(2) 6,

preferably through reactive ion etching. Using the etched

SiO(2) layer as mask and a highly selective reactive ion

etchant, such as SF(6), etch annular trenches in silicon

to a depth typically 0.5 Mum larger than the thickness

of N- epitaxial layer 4. The cross-sectional structure

at this stage is shown in Fig. 2.

4. Remove remnant SiO(2) 6 and preferably grow about 600

Angstroms thermal SiO(2) 8 at the silicon surface.

5. Fill the trench regions with an insulating material 10, such

as SiO(2). When SiO(2) is used as the trench-filling

insulator, a several micrometer thick SiO(2) layer is

typically deposited pyrrolytically. A planarizing layer of

photoresist is then typically coated and the wafer surface

is subjected to reactive ion etching using gases which

etch the photoresist and SiO(2) at practically the same

rate. Etching is stopped when the structure of Fig. 3

results.

6. Deposit a film of the desired Schottky barrier metal, e.g.,

platinum. Subject the wafer to an appropriate sintering

heat cycle. In the case of platinum, platinum silicide

is formed at the bare silicon surface. Unreacted

platinum is then...