Browse Prior Art Database

Eight Device Exclusive OR CMOS Circuit

IP.com Disclosure Number: IPCOM000050335D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Dearden, ZT: AUTHOR [+2]

Abstract

An eight-device exclusive OR CMOS circuit is disclosed which eliminates the problem of the effect of threshold voltage drops on the output levels of a CMOS exclusive OR circuit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Eight Device Exclusive OR CMOS Circuit

An eight-device exclusive OR CMOS circuit is disclosed which eliminates the problem of the effect of threshold voltage drops on the output levels of a CMOS exclusive OR circuit.

The circuit is shown in the figure with the P channel FET device 1 and the N channel FET device 2 serving as a first CMOS inverter and the N channel FET device 3 and the P channel FET device 4 serving as a second CMOS inverter. The source of P channel device 1 is connected to the V potential, and the drain thereof is connected to a first node 9. The drain of the N channel FET device 2 is connected to the first node 9, and its source is connected to ground potential. The source of the N channel FET device 3 is connected to ground potential, and the drain thereof is connected to a second node 10. The drain of the P channel FET device 4 is connected to the node 10 and its source is connected to V voltage. The gates of the FET devices 1 and 2 are connected in common to the binary input variable A. The gates of the FET devices 3 and 4 are connected in common to the other binary input variable B. The N channel FET device 5 and the P channel FET device 6 are connected as a transfer pair. The N channel FET device 7 and the P channel FET device 8 are connected as a second transfer pair. The drain of the N channel FET device 5 is connected in common with the source of the P channel FET device 6 to the binary input variable B. The source of the N channel FET device 5 and the drain of the P channel FET device 6 are connected in common to the output node C. The gate of the N channel FET device 5 is connected to the first node 9, and the gate of the P channel FET device 6 is connected to the A input variable. The drain of the N channel FET device 7 is connected in common with the source of the P channel FET device 8 to the node 10. The source of the N channel FET device 7 is connected in common with the drain of the P channel FET device 8 to the output node C. The gate of the N channel FET device 7 is connected in common with the gate for the P channel device 6 to the binary input variable A. The gate of the P channel FET device 8 is connected in common with the gate of the N channel FET device 5 to the first node 9.

The following truth table illustrates the operation of the circuit in the figure. Truth Table

A B C

1 1 0

0 1 1

1 0 1

0 0 0.

When the binary input A is a positive voltage indicating a binary one and the binary input B is a positive voltage indicating a binary one, devices 2 and 3 are on and devices 1 and 4 are off. The node 9 is at ground potential and therefore device 5 is off and device 8 is on. Since the binary input variable A is positive, device 6 is off and device 7 is on. The low voltage on node 10 is therefore propagated through both FET devices 7 and 8 and serves as a binary zero value at the output node C.

1

Page 2 of 3

When the A input va...