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Module Test with Computer Simulator and Random Pattern Generator

IP.com Disclosure Number: IPCOM000050339D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Rossero, H: AUTHOR

Abstract

This test bed 10 tests several modules at the same time using a random pattern generator and a computer which has been programmed to simulate a good module.

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Module Test with Computer Simulator and Random Pattern Generator

This test bed 10 tests several modules at the same time using a random pattern generator and a computer which has been programmed to simulate a good module.

A common random pattern generator 12 provides identical test patterns to the inputs of each module 14. The output data of each module 14 are collected and compressed by a signature collector 16. The random pattern generator 12 also provides the very same sequence of patterns to a computer 18. The computer 18, via a program determined by the modules part number, in conjunction with data from a data base, is programmed to simulate the response of the type of module being tested. A common timing circuit 20 (Clock Timer A,B,C) provides synchronized clock pulses to the simulator 18, the modules under test and the random pattern generator. The result of each signature collector is then compared with the signature generated by the good module simulator 18.

At any n count of sequential patterns at which a module fails the signature comparison, the contents of the output shift registers of the failing module may be compared with the contents of the shift registers of a non-failing module, and a defective chip or chips on the failing module identified.

After each signature compare, the sequential pattern count is advanced if the compare is successful. If a compare does not match, then the pattern count is stopped to allow scanning of the shift registers....