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Browse Prior Art Database

Target Address Branch History Table

IP.com Disclosure Number: IPCOM000050347D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR

Abstract

A Target Address Branch History Table (TAHT) added to the mechanism shown in U.S. Patent 4,200,927 can help to improve the accuracy of guesses for the conditional branches (BC/BCR). The table is based upon the history of target address from BC/BCR.

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Target Address Branch History Table

A Target Address Branch History Table (TAHT) added to the mechanism shown in U.S. Patent 4,200,927 can help to improve the accuracy of guesses for the conditional branches (BC/BCR). The table is based upon the history of target address from BC/BCR.

A new way is discovered for implementing a decode table of target address history for BC(R), which is similar to the decode branch history table described in the preceding article. That method uses the instruction address of BC(R) to address the decode table. The method described here uses the target address of BC(R) to address the decode table.

A 2k-bit decode table is maintained on past history of target address from BC and BCR. The target address of a branch, hashed with its mask, is used to read out the history bit of the decode table at decode time. The history bit determines the BC(R) branch guess. At the end of execution of the branch of BC(R), the history bit of the decode table is updated accordingly.

In the figure, the D field 1 of BC, hashed with its mask 2, is used to read out the history bit of the TAHT 3, and the hashed address of the decode table is kept at TAHTA Register (Target Address History Address Register) 4, which has a dimension of 11 bits. Each TAHTA Register 4 is associated with one of the instruction registers shown in the cited patent. The contents of TAHTA Register 4 will be used as an address to write a bit to the decode table 3 at the end of the executi...