Browse Prior Art Database

Generation of Fault Oriented Test Sequence

IP.com Disclosure Number: IPCOM000050354D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Brown, A: AUTHOR [+4]

Abstract

The generation of a fault oriented test sequence for a sequential circuit is shown in the figures. It is accomplished by successfully generating three components: Homing Sequence, Test Condition, and Drive-Out Sequence. The Generation of the Fault-Oriented Test Sequence (GEFTS) algorithm takes as imput, the block (Boolean) level description of the logic, and a specification of the fault in the logic. The input is transformed to a high level model- the Logic Flowgraph (LFG). This particular flowgraph is called the "Good Machine LFG" (GMLFG). The description of the fault is used to modify the GMLFG by reflecting the existence of a constant level logical value at the pin associated with the fault. The modified model is the "Bad Machine LFG" (BMLFG).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

Generation of Fault Oriented Test Sequence

The generation of a fault oriented test sequence for a sequential circuit is shown in the figures. It is accomplished by successfully generating three components: Homing Sequence, Test Condition, and Drive-Out Sequence. The Generation of the Fault-Oriented Test Sequence (GEFTS) algorithm takes as imput, the block (Boolean) level description of the logic, and a specification of the fault in the logic. The input is transformed to a high level model- the Logic Flowgraph (LFG). This particular flowgraph is called the "Good Machine LFG" (GMLFG). The description of the fault is used to modify the GMLFG by reflecting the existence of a constant level logical value at the pin associated with the fault. The modified model is the "Bad Machine LFG" (BMLFG).

Subsequently, the next-state functions of the GMLFG and the BMLFG are compared for functional equivalence. This is possible using known techniques, since these functions in the two models are assumed to have one to one correspondences. If this comparison shows that each pair of next-state functions is equivalent, then the indication is that the fault under consideration does not affect any of the functional variables in the logic (i.e., storage elements or primary outputs), and is therefore not detectable. If, however, the result of the comparison is a non-empty function in a sum of products form, then each of these products is saved as one Test Condition (TC) needed to at least...