Browse Prior Art Database

Dual Chip Semiconductor Module

IP.com Disclosure Number: IPCOM000050388D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Rogers, DF: AUTHOR

Abstract

This article concerns a technique for providing substantial freedom of interconnection between semiconductor chips on a dual-chip module.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 82% of the total text.

Page 1 of 2

Dual Chip Semiconductor Module

This article concerns a technique for providing substantial freedom of interconnection between semiconductor chips on a dual-chip module.

A dual-chip module comprises two chip sites with interconnections between the chip sites and between each chip site and the module pins. However, personalization of the wiring on the module is hampered by the lack of multilevel wiring facilities and, in consequence, the possible chip to chip I/O connections. This, in turn, constrains the chip designer.

This disadvantage is overcome by interposing a passive two-level I/O connection chip between the functional chips. The I/O connection chip may be personalized as desired, thus providing a high degree of flexibility in chip to chip connections.

An example is shown in the figure. IC1 and IC2 are the Chip sites for the two functional chips, and I/O is the site of the two-level I/O connection chip. The module terminals are shown at T. It will be noted that the outer half of each functional chip IC1 and IC2 connects directly to module pins T, while the inner half of each connects to the other functional chip via the I/O chip. This has the additional advantage of permitting simple replacement of the two chips IC1 and IC2 by a single centrally mounted functional chip having the same overall function as the combined function of the two chips IC1 and IC2 should this be desired. This is because the single chip would have the same chip pad to module pin wiring...