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Chip Attachment Structure for High Performance, Efficiently Cooled Semiconductor Chip Carriers

IP.com Disclosure Number: IPCOM000050401D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Ho, CW: AUTHOR [+2]

Abstract

One chip to package joining approach is the flip-chip C-4 solder ball joint. This approach has unique advantages and disadvantages. The advantages are: capability for batch fabrication, high I/O pin count due to area array and small pin size, good reliability, and low pin inductance and capacitance. The notable disadvantages are the difficulty with which heat is removed from the back side of the chip and the potential damage to the rigid lead tin C-4 solder balls arising from lateral stresses created by different thermal expansion rates in the chip and substrate materials. Future VLSI (very large scale integration) high performance semiconductor chips will require increased power dissipation, increased pin count, smaller pin grids and, therefore, smaller pins.

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Chip Attachment Structure for High Performance, Efficiently Cooled Semiconductor Chip Carriers

One chip to package joining approach is the flip-chip C-4 solder ball joint. This approach has unique advantages and disadvantages. The advantages are: capability for batch fabrication, high I/O pin count due to area array and small pin size, good reliability, and low pin inductance and capacitance. The notable disadvantages are the difficulty with which heat is removed from the back side of the chip and the potential damage to the rigid lead tin C-4 solder balls arising from lateral stresses created by different thermal expansion rates in the chip and substrate materials. Future VLSI (very large scale integration) high performance semiconductor chips will require increased power dissipation, increased pin count, smaller pin grids and, therefore, smaller pins. These factors will significantly increase mechanical and thermal strains on the chip, and the high thermal resistance in the C-4 path will severely aggravate the heat-removal problem, thus leading to complex heat-removal systems.

Other VLSI applications, particularly in memory and microprocessors, will use air cooling to the maximum extent possible.

This will require a chip mounting which lends itself to the limitations of this form of heat removal, and which also allows the high I/O pin count capability of the C-4 along with a limitation on the package inductance in order to permit good simultaneous switching ability.

This article describes a back-side chip bonding approach which contains novel modifications that permit low-cost chip I/O attachment methods, such as tape bonding, decal or beam lead, and concurrently provides for extended pin displacement from neutral position (DNP) capability, extended air-cooling capability, and in the same module decoupling of power distribution system transients from the logic signal lines. With current back-bonded peripheral I/O chips, a major factor limiting system performance is the simultaneous switching (or DI noise) due to lead and package inductances. Another is that back-bonded chips on a thin film substrate will take away excessive module area for wiring. Furthermore, individual chip joining and removal has to be provided for on a multi-chip module and the high chip I/O count requirement has to be met.

Technology available commercially in the semiconductor industry (*) provides the capability of perimeter I/O connection with a linear density with I/O's on 100 Mum centers. With a chip 4 mm in size 2 rows of perimeter I/O with a 4-mil density should provide 320 I/O's which can accommodate 100 Mum...