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Method to Combine High Voltage Analog Bipolars with High Speed MTL on a Thin Epitaxial Layer

IP.com Disclosure Number: IPCOM000050402D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Tang, DD: AUTHOR

Abstract

This article relates generally to integrated circuits and more specifically to integrated circuits wherein high voltage analog bipolar transistors and high density, high speed, digital bipolar transistors are formed in the same epitaxial layer.

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Method to Combine High Voltage Analog Bipolars with High Speed MTL on a Thin Epitaxial Layer

This article relates generally to integrated circuits and more specifically to integrated circuits wherein high voltage analog bipolar transistors and high density, high speed, digital bipolar transistors are formed in the same epitaxial layer.

High voltage analog bipolar integrated circuits are usually fabricated on epi (epitaxial) films of approximately 10 microns thickness so that the high voltage at the collector can be absorbed by a depletion region in the epitaxial layer. The thick epi process used to fabricate such devices is not compatible with high performance digital bipolar circuits which are designed to be operated at very low voltage to minimize power dissipation. These low power devices use epitaxial layers less than 1 Mum in thickness. In addition, transistors on a thick epi layer require very deep and therefore very wide isolation regions, which drastically degrades the density of digital circuits. Furthermore, the performance of circuits like Merged Transistor Logic (MTL) (which can still be very dense because it does not need isolation) is very poor due to the thick epi layer.

This article describes a method and resulting structure whereby high voltage analog bipolar integrated circuits (ICs) can be fabricated with low voltage digital ICs on the same chip. This is made possible by absorbing the high collector voltage at the collector reach-through with a depleted epi region situated between the collector contact and the n+ sublayer of the npn transistor, as shown in the figure.

In the figure, a high voltage analog device 1 is shown on the right-hand side. An npn bipolar transistor 2 is formed in a thin epitaxial layer disposed on a substrate 3. A lateral FET device 4, formed from...