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MOSFET with Self Aligned Buried Contacts

IP.com Disclosure Number: IPCOM000050403D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR

Abstract

This article describes a self aligned MOSFET structure and a fabrication method therefor using only four masking steps. In the first step, as shown in Fig. 1, recessed oxide regions 10 are formed in a p- substrate 12 with field boron ion implantation 14. Then layers of oxide 16, nitride 18, oxide 20, polysilicon (or polycide) 22, and oxide 24 are formed on top of the substrate 12 using a first mask. Next using a photoresist layer 26 as a second mask, the oxide 24, polysilicon 22 and oxide 20 are reactive ion etched, as shown in Fig. 2. These oxide layers 24 and 20 are wet etched to form an undercut. A thin layer of tungsten is deposited, and then the photoresist is stripped, lifting off the tungsten which had bean deposited on the resist, leaving the areas of tungsten 28, as shown in Fig. 3.

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MOSFET with Self Aligned Buried Contacts

This article describes a self aligned MOSFET structure and a fabrication method therefor using only four masking steps. In the first step, as shown in Fig. 1, recessed oxide regions 10 are formed in a p- substrate 12 with field boron ion implantation 14. Then layers of oxide 16, nitride 18, oxide 20, polysilicon (or polycide) 22, and oxide 24 are formed on top of the substrate 12 using a first mask. Next using a photoresist layer 26 as a second mask, the oxide 24, polysilicon 22 and oxide 20 are reactive ion etched, as shown in Fig. 2. These oxide layers 24 and 20 are wet etched to form an undercut. A thin layer of tungsten is deposited, and then the photoresist is stripped, lifting off the tungsten which had bean deposited on the resist, leaving the areas of tungsten 28, as shown in Fig. 3. The nitride layer 18, oxide layer 24, and oxide layer 16 not covered by tungsten 28 are etched, and then the tungsten 25 is stripped, as shown in Fig. 4. A layer of n polysilicon 30 is then deposited over the structure, as shown in Fig. 5, and then a blanket reactive ion etch is performed, removing the polysilicon 30 everywhere except on the sidewalls, as shown in Fig. 6. Source and drain regions 32 and 34 are formed, and oxide 36 is grown, as shown in Fig. 7. The nitride 18 and oxide 16 in the gate region are etched, and the gate oxide is regrown. Boron is implanted to form the desired channel doping 38, and contact holes 40 are opene...