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Josephson Circuit Fabrication Process

IP.com Disclosure Number: IPCOM000050407D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Faris, SM: AUTHOR

Abstract

Preparing and testing a full-wafer Josephson junction, and subsequently subtractively etching a pattern to define individual junctions and conductors, increases yield and permits the manufacture of complex integrated devices in Josephson technology. The most crucial fabrication step in Josephson technology is the formation of the tunnel barrier and the reproducible control of the current density and its variations. In present practice, the tunnel barrier fabrication step is preceded by several steps involving photo-resist layers and SiO which are detrimental to reproducibility, reliability, and the ability to cycle the junctions between room temperatures and cryogenic temperatures.

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Josephson Circuit Fabrication Process

Preparing and testing a full-wafer Josephson junction, and subsequently subtractively etching a pattern to define individual junctions and conductors, increases yield and permits the manufacture of complex integrated devices in Josephson technology. The most crucial fabrication step in Josephson technology is the formation of the tunnel barrier and the reproducible control of the current density and its variations. In present practice, the tunnel barrier fabrication step is preceded by several steps involving photo-resist layers and SiO which are detrimental to reproducibility, reliability, and the ability to cycle the junctions between room temperatures and cryogenic temperatures. In the circuit fabrication process of this article, a "backwards" approach is used incorporating full wafer processing, in which a huge tunnel barrier junction is formed over the entire chip and is then patterned to produce the individual tunnel junctions of the various devices.

There are two distinct processes:

1) a barrier formation process (BFP), and

2) a circuit fabrication process (CFB).

Barrier Formation Process (BFP).

Fig. 1 is a view of a cross-section of a multilayer wafer 10. The BFP produces junctions with the desired current densities and minimum spreads in the current densities, due to a minimum amount of handling of the wafer, no contamination due to photoresist steps, and no SiO which would cause backscattering. Silicon substrate 12 has a thermally grown oxide layer 14. A first metal layer M1A (Nb ground plane layer 16) is deposited and covered by insulating layer 18. Insulating layer 18 is made by anodizing the Nb ground plane to form Nb(2)0(5) (I1A) and then depositing a layer (I1B) of SiO. A layer 20 forming the base electrode M2A is deposited so that it covers the entire wafer 10. Layer 20 can be thin enough (approximately 700 Angs.) so that good thermal cycling will result, especially since strain gradients are eliminated because SiO is not required to define the individual tunnel junctions. It is now possible to test and detect early M2A-M1A shorts and reject such wafers. Testing is preferably by a number of probing actions at a number of test sites located in kerf areas which are to be lost in subsequent dicing operations. This testing step increases the overall fabrication yield. After testing for shorts, tunnel barrier 22 is formed on those wafers which have no M2A-M1A electrical...