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Method for Etching Via Holes in SiO

IP.com Disclosure Number: IPCOM000050412D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Gegenwarth, RE: AUTHOR

Abstract

When SiO is deposited by evaporation over thin film patterns having steep edges, the SiO in the vicinity of the step is of a lower density than the remaining SiO and etches more rapidly in HF. This effect is used to etch via holes in SiO.

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Method for Etching Via Holes in SiO

When SiO is deposited by evaporation over thin film patterns having steep edges, the SiO in the vicinity of the step is of a lower density than the remaining SiO and etches more rapidly in HF. This effect is used to etch via holes in SiO.

The technique is followed using a disposable material to form the steep edge and the via area or shape. In Fig. 1, a silicon wafer 10 has a first wiring pattern comprised of Nb layers 12 having gently sloped edges. The vias can be patterned by lifting off A1, leaving a steep walled stud 14 on top of the Nb land
12.

After depositing SiO on top of the structure of Fig. 1, the wafer is dipped into HF for one or two seconds, forming a crevasse 16 in the SiO layer 18 around the A1 stud 14, as shown in Fig. 2.

A1 stud 14 is etched by an etchant which will not attack Nb land 12 or the SiO. The SiO cap 20 will fall off and be washed away, leaving a via hole 22, as shown in Fig. 3.

This process can be repeated to form several layers of interconnected Nb. It could also be used for other metals, provided that a stud material is selected which is compatible with the underlying land material, so that the etchant used to remove the stud and SiO cap does not attack the underlying land.

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