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Partitioned Page Transfer From an Electronic Drum

IP.com Disclosure Number: IPCOM000050430D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Franaszek, PA: AUTHOR

Abstract

In a system operating in the synchronous mode (i.e., operation of the affected CPU is halted given a page fault to a specific device such as drum), it is desirable to restart the processor as soon as the desired line (unit of transfer into the cache) becomes available. A system is described providing a separate addressing path to pages which are in the process of being transferred from the drum to thereby permit quick access to the information being transferred without pages in the process of being transferred from the drum.

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Partitioned Page Transfer From an Electronic Drum

In a system operating in the synchronous mode (i.e., operation of the affected CPU is halted given a page fault to a specific device such as drum), it is desirable to restart the processor as soon as the desired line (unit of transfer into the cache) becomes available. A system is described providing a separate addressing path to pages which are in the process of being transferred from the drum to thereby permit quick access to the information being transferred without pages in the process of being transferred from the drum.

An alternative to the current design would be to implement main memory in a manner analogous to conventional caches, with valid/invalid bits for each line (cache replacement unit) in each page. This would also permit accesses to a given line as soon as its transfer is complete, but such a system would be impractical because the additional logic for the valid/invalid bits would be overly expensive, especially for very large memories. Also, there would be a problem of interference between multiple CPUs given that one or more are waiting for a line transfer.

According to the subject system shown in the figure, the special addressing path includes one or more page input address registers 10 associated with each cache 12. Each cache access results in comparing the requested line real address on line 14 from the CPU 16 with that of the pages on line 18 from the drum controller 20 in the process of b...