Browse Prior Art Database

Engineering Change Verification

IP.com Disclosure Number: IPCOM000050435D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Epstein, ME: AUTHOR [+2]

Abstract

One of the major problems of the industry is the removal of "bugs" from design algorithms, whether in the form of hardware or of software. Location of design errors in hardware has been infinitely more successful than for software. Nevertheless, the capacity of present hardware algorithms for verification is still barely sufficient for current machines. Essentially, the verification algorithms consider TWO machines, the "new" and the "old"; it then considers these as a single design, roughly twice as large.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 1

Engineering Change Verification

One of the major problems of the industry is the removal of "bugs" from design algorithms, whether in the form of hardware or of software. Location of design errors in hardware has been infinitely more successful than for software. Nevertheless, the capacity of present hardware algorithms for verification is still barely sufficient for current machines. Essentially, the verification algorithms consider TWO machines, the "new" and the "old"; it then considers these as a single design, roughly twice as large. The computations nowhere can take advantage of the similarity of the two designs; in the Engineering-Change algorithm (EC-algorithm) as described here, it is assumed that the designs are identical except for a small portion, this being caused by an engineering change; these differences are then considered as if they were "failures" and the D- algorithm, modified as described here, is invoked to compute a test distinguishing the two versions of the design if, and only if, such a test exists, in a small fraction of the time required for previous algorithms.

The following description assumes familiarity with the D-algorithm (1). For simplicity and no loss of generality, assume that each logic block, primitive, is an AND-invert-- the program will assume only 1-,2-,3-and 4-input blocks. In the second place, assume that each EC consists of a set (assemblage) of changes to the interconnections between individual blocks, either through...