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Use of Load Bypass on Load Multiple Instruction to Reduce Address Generation Interlock Delays

IP.com Disclosure Number: IPCOM000050437D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Rao, GS: AUTHOR

Abstract

A method is shown of using the LOAD BYPASS path for interlocks caused by LOAD MULTIPLE (LM) instructions that is simple to implement and which reduces the delay for approximately 80 percent of the LM. Most of the interlocks caused by LM instructions are due to the register loaded last as specified in the instruction. An example is shown below. L D, 2FC(0,0) LM C,D, 088(D,0) (Load reg. C and D) BALR E,D (Interlock on reg. D).

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Use of Load Bypass on Load Multiple Instruction to Reduce Address Generation Interlock Delays

A method is shown of using the LOAD BYPASS path for interlocks caused by LOAD MULTIPLE (LM) instructions that is simple to implement and which reduces the delay for approximately 80 percent of the LM. Most of the interlocks caused by LM instructions are due to the register loaded last as specified in the instruction. An example is shown below. L D, 2FC(0,0)

LM C,D, 088(D,0) (Load reg. C and D)

BALR E,D (Interlock on reg. D).

The method consists of deriving the storage address from which the last register is to be loaded when an LM is decoded. This is routinely done in high performance machines in order to detect page crossings for exception handling. This is set into a 24-bit Last Address Register (LAR). The identity of the general- purpose register (GPR) to be loaded as specified in the LM instruction also is set into a register, last general-purpose register (LGPR). This occurs every time an LM instruction is decoded.

When a GPR interlock (address generation interlock (AGI)) is detected, a check is made to determine if the register in LGPR is the cause. If it is, then a fetch is made to the address in LAR as for a LOAD instruction with LGPR as the target register and LAR as the effective storage address. The intent is to create a ghost LOAD instruction so that the LOAD BYPASS path and circuitry can be set in motion. This ghost load is never permitted to go to the execu...