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Access Rate/Availability Improvement Logic for Dynamic Memories

IP.com Disclosure Number: IPCOM000050453D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Grimes, WD: AUTHOR [+3]

Abstract

A technique is described which improves system dynamic memory accessing rates. Some degradation may occur in a system due to halting of memory accesses to perform memory refreshes. The major performance degradation when using dynamic memories is in the multiplexing and between memory accessing and memory refreshing, with a normal break-in refresh arrangement in which the system performs some memory cycles and then is halted so that one refresh can be performed. The method describerd here refreshes memory in such a manner that breaking-in with refreshes and halting accesses is prevented. In some systems, memory utilization may approach 100 percent.

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Access Rate/Availability Improvement Logic for Dynamic Memories

A technique is described which improves system dynamic memory accessing rates. Some degradation may occur in a system due to halting of memory accesses to perform memory refreshes. The major performance degradation when using dynamic memories is in the multiplexing and between memory accessing and memory refreshing, with a normal break-in refresh arrangement in which the system performs some memory cycles and then is halted so that one refresh can be performed. The method describerd here refreshes memory in such a manner that breaking-in with refreshes and halting accesses is prevented. In some systems, memory utilization may approach 100 percent. This results in an improvement of the system access rate/availability by the formula: The "useful access duty cycle of the method described here" divided by the "useful access duty cycle of the break-in method" minus "unity" = 8/8 / 7/8 - 1 = 1.143 - 1 = 14.3 percent

The memory access rate/availability is improved by providing logic to perform refresh on either half of the memory while the other half is accessing memory, and vice versa. This results in refreshes and accesses being performed in parallel rather than in series; thus, refreshes have no impact on the access rate. This technique is more effective in sequential accesses of contiguous addresses since the words selected are odd even odd, etc. When selecting sequences of addresses, this invention guarantees completely hidden refreshes. Processor Instruction Fetches and Cycle Steal data transfers are the most common methods (most used) of storage accesses. Both these methods have their addressing patterns set to sequential words in main storage.

The memory is divided into two equal halves, designated Bank A and Bank
B. When a memory access is performed on one bank, the alternate bank is refreshed at the same time, in parallel, and the refreshed bank is remembered, preventing the same bank from being refreshed again during the 8-cycle period. When a memory access is performed on the alternate bank, the first bank is refreshed in parallel with the access, and the first bank's having been refreshed is also remembered, preventing its being refreshed again during the 8-cycle period. A flowchart is shown in Fig. 1. From process block 1, "START", decision diamond 2, "END OF 8-CYCLE PERIOD?", is encountered. If this present cycle is not the eighth cycle in this period, exit to 3, "ACCESS BANK?", which asks, "Is Bank A or Bank B to be accessed?" The address LSB (Least Significant Bit) determines the bank selection. If Bank A is being accessed, 4 asks, "Has Bank B been refreshed during this 8-cycle period?" If no, 5 refreshes Bank B in parallel with Bank A's access; thus, a refresh has been performed without halting accesses. Block 6 sets the "BANK B REFRESHED" latch which remembers that Bank B has been refreshed. Via connector M, return to 2 and then to 3, where again the LSB d...