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Vertical Parity Generator for Two Dimensional Parity

IP.com Disclosure Number: IPCOM000050454D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR [+2]

Abstract

A scheme is described for reducing the logic necessary for the generation of parity in conjunction with a two-dimensional parity arrangement. New vertical parity is generated from the old data, the new data, and the old vertical parity. Error correction code (ECC) is defined as a data scheme in a computer design which detects and corrects errors in data flow. Two-dimensional parity is an ECC in which single bit errors are corrected. Horizontal parity is used to detect errors, and vertical parity is used to datect and correct particular bits in a byte.

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Vertical Parity Generator for Two Dimensional Parity

A scheme is described for reducing the logic necessary for the generation of parity in conjunction with a two-dimensional parity arrangement. New vertical parity is generated from the old data, the new data, and the old vertical parity. Error correction code (ECC) is defined as a data scheme in a computer design which detects and corrects errors in data flow. Two-dimensional parity is an ECC in which single bit errors are corrected. Horizontal parity is used to detect errors, and vertical parity is used to datect and correct particular bits in a byte.

Fig. 1 shows a generalized ECC implementation. Sixteen data bits plus two parity bits are received from the system 1. Six check bits are generated by block 2 from 16 data bits and stored in the storage 3 as 16 6 bits. In a read operation, the six check bits are reformed by block 4 from 16 data bits read from memory 3. Six syndrome bits are generated by block 5 from stored check bits and the reformed check bits. The syndrome bits are decoded by block 6 to determine the single bit or multiple bits in error and to determine which data bit is in error. The bit in error is corrected by block 7, the parity generated by block 8, and (16+2) bit words returned to the system.

In particular, the arrangement involves the reduction of the circuits from those shown in Fig. 2, involving a prior representative vertical parity generator, to the configuration shown in Fig. 3 with a consequent reduction from 252 circuits down to 90, that is, a total reduction of 162 circuit counts. There is a resulting reduction in delay involved in the circuits and performance enhancement. Also, the circuitry is involved in a main internal loop used in every memory cycle. In Fig. 2, an Exclusive OR function is performed on the old data...