Browse Prior Art Database

Parity Generate and Check Circuit

IP.com Disclosure Number: IPCOM000050458D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Tutt, WE: AUTHOR

Abstract

Conventional data parity on a parallel data bus provides error checking for each data transfer across the data bus. However, on attachments which must serialize data, such as a disk unit, the parity is checked on the parallel data, the parity bit is discarded, and the data is serialized and sent to the disk. Other check codes such as cycle redundancy check (CRC) are not computed until after the serialization process. This means that potential data errors due to noise, hardware malfunctions, and so forth, will occur undetected until noticed in the actual data. On attachments which receive serialized data and deserialize and transfer it across a parallel data bus, the problem is the same. The serial data is checked for a correct CRC before the deserializer.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Parity Generate and Check Circuit

Conventional data parity on a parallel data bus provides error checking for each data transfer across the data bus. However, on attachments which must serialize data, such as a disk unit, the parity is checked on the parallel data, the parity bit is discarded, and the data is serialized and sent to the disk. Other check codes such as cycle redundancy check (CRC) are not computed until after the serialization process. This means that potential data errors due to noise, hardware malfunctions, and so forth, will occur undetected until noticed in the actual data. On attachments which receive serialized data and deserialize and transfer it across a parallel data bus, the problem is the same. The serial data is checked for a correct CRC before the deserializer. After deserialization, parity is generated from the parallel data, appended to it, and transferred across the parallel bus. Again, any data errors which occur in the deserialization process will go.undetected by the hardware attachment.

The circuit shown in the figure represents a concept which solves the problems noted above. This circuit is designed for an attachment which interfaces a 16-bit plus parity bit Read/Write storage interface with a disk file encode/decode circuit, which is a serial interface. The circuit detects data errors which occur during a bus transfer cycle as well as the serialization/deserialization process.

For operations requiring data to be transferred from the parallel bus to a serial device, data bus parity will be captured in a latch for each byte of data. This parity latch content will be maintained during the serialization process. As the parallel data is being serialized, parity will be computed for each byte from the serialized data. This parity bit will then be compared to the parity latch content. If the comparison indicates both parity bits are the same, the data is considered to be correct. If the comparison indicates both parity bits are different, the data is considered to be in error. For operations requiring data to be transferred from a serial device to a parallel bus, parity must be generated. This is done by computing the parity from the serial data which is entering the deserializer. After deserialization of each byte, this computed parity bit is appended to the parallel data and transferred across the bus with the data.

The implementation of the circuit shown in the figure was for a disk unit attachment in which the encode/decode electronics requires or provides data bytes serialized 2 bits at a time. The parallel bus transfers two bytes of data to or from a read/write memory along with an odd parity bit for ea...