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Improved SiO(2) Etchant to Reduce FET Metal Gate

IP.com Disclosure Number: IPCOM000050492D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Esch, RP: AUTHOR [+2]

Abstract

Parasitic capacitance exists in insulated gate field-effect transistors (IGFETs) where the gate electrode overlaps the source and drain diffusions. The circuit performance of such devices in terms of switching speed and rise and fall times is decreased relative to optimum performace. This is a particular problem to metal gate IGFET devices since the gate formation process does not provide self-alignment with the source and drain of the device. This problem has been addressed in the prior art in U.S. Patent 4,056,825, wherein metal gate overlap of the diffused source or drain regions is reduced by increasing the oxide thickness over the diffused regions through selective oxide regrowth techniques.

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Improved SiO(2) Etchant to Reduce FET Metal Gate

Parasitic capacitance exists in insulated gate field-effect transistors (IGFETs) where the gate electrode overlaps the source and drain diffusions. The circuit performance of such devices in terms of switching speed and rise and fall times is decreased relative to optimum performace. This is a particular problem to metal gate IGFET devices since the gate formation process does not provide self-alignment with the source and drain of the device. This problem has been addressed in the prior art in U.S. Patent 4,056,825, wherein metal gate overlap of the diffused source or drain regions is reduced by increasing the oxide thickness over the diffused regions through selective oxide regrowth techniques. A different approach to solving this problem is described, wherein an improved silicon dioxide etchant will provide an increased taper angle for the silicon dioxide over the source and drain diffusions.

In existing metal gate MOSFET processes, the silicon dioxide layer in both the field region and the gate region is coated with a thin layer of phosphosilicate glass which serves as a contaminant gettering layer. When the silicon dioxide layer is etched with a conventional etchant such as a 7:1 buffered hydrofluoric acid solution, the resultant taper angle Theta1 will be from 18 to 20 degrees.

A new etchant solution formulated as 100 grams of reagent grade tris (hydroxymethyl) aminomethane, commonly known as tris, is added i...