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Reduced Diffusion Capacitance in Logic Macros with Droppable Inputs

IP.com Disclosure Number: IPCOM000050496D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 66K

Publishing Venue

IBM

Related People

Burke, RD: AUTHOR [+2]

Abstract

An FET circuit design structure is disclosed which enables the circuit designer to reduce the diffusion capacitance in logic macros which have droppable inputs.

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Reduced Diffusion Capacitance in Logic Macros with Droppable Inputs

An FET circuit design structure is disclosed which enables the circuit designer to reduce the diffusion capacitance in logic macros which have droppable inputs.

A logic macro, for example, a four-input NOR logic function, as is shown in the electrical schematic diagram of Fig. 1 and as is shown in the layout of Fig. 2, is embodied with eight enhancement mode FET devices and two depletion mode FET devices numbered one through 10, as illustrated. The conventional practice in designing logic macros is to provide a separate logic macro for each numerical input value; for example, if a family of NOR circuits in a particular circuit library had 2, 3, 4, 5 and 6 input NORs, then five separate logic macro books would have had to be stored in the circuit library to accommodate the various options to be applied by the circuit designer.

Another approach to logic macro design has been to provide a single logic macro for each of several numerical input options; for example, in a four-input NOR, where the circuit designer was given the option of having a three-input or two-input NOR, then the gates for some of the droppable FET devices in the macro could be selectively deleted. A problem which has arisen with this conventional approach is that the associated source and/or drain diffusions for the dropped FET devices remain connected to the other sources and/or drains which are still being used in the macro circuit, and thus additional diffusion capacitance is unnecessarily coupled into the circuit.

The reduced diffusion capacitance invention described herein provides a layout and contact structure which enables the circuit designer to optionally drop unused FET devices in the logic macro and automatically disconnect the unused sources and/or drains of those dropped devices from the balance of the circuit, so as not to unnecessarily load the balance of the circuit with the diffusion capacitances of the dropped devices.

The layout of the four-input NOR macro shown in Fig. 2 illustrates the invention. FET transistors 2 and 7 operate off the same polycrystalline silicon gate AO. FET device 2 has a drain diffusion D(2) and a source diffusion S(23). FET device 7 has a drain diffusion D(7) and a source diffusion S(23). Similarly, FET devices 3 and 8 operate off the same polygate A1. FET device 3 has a source diffusion S(23) and a drain diffusion D(34), and FET device 8 has a source diffusion S(23) and a drain diffusion D(89). FET devices 4 and 9 operate off the same polygate A2. FET device 4 has a drain diffusion D(34) and a source diffusion S(45), and FET device 9 has a drain diffusion D (89) and a source diffusion S(45). FET devices 5 and 10 operate off the same polygate A3. FET device 5 has a source diffusion S(45) and a drain diffusion D(5), and FET device 10 has a source diffusion S(45) and a drain diffusion D(10).

The drain diffusions D(2), D(34), and D(5) are connected in commo...