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Browse Prior Art Database

Glitchless Delta Vector Generator

IP.com Disclosure Number: IPCOM000050498D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Marple, WP: AUTHOR

Abstract

In a conventional delta vector generator, there are three modes of operation: (1) an initial position is loaded and the output is caused to slew rapidly to this position; (2) the output is made to ramp at a constant, predetermined rate to a point equal to the original position plus a desired displacement; and (3) the output is caused to dwell at the present position while calculations are performed or when new data is to be loaded.

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Glitchless Delta Vector Generator

In a conventional delta vector generator, there are three modes of operation:
(1) an initial position is loaded and the output is caused to slew rapidly to this position; (2) the output is made to ramp at a constant, predetermined rate to a point equal to the original position plus a desired displacement; and (3) the output is caused to dwell at the present position while calculations are performed or when new data is to be loaded.

In the prior art, the output voltage is produced across a capacitor which is connected to a conventional voltage to current converter through a conventional FET switching device. For condition (2) above the FET switch is closed, applying a constant current to the capacitor producing a voltage ramp. For condition (3) above the FET switch is opened, removing the current and causing the capacitor voltage to dwell until the FET switch is again closed. The prior art contains two primary sources of error: non-linearity in the voltage to current converter which is dependent on the magnitude of the capacitor voltage, and charge injection into the capacitor when the FET switch is turned on or off. These errors are cumulative, causing increasing positional inaccuracies as increasing numbers of vectors are chained upon one another.

The circuit shown in the figure overcomes these sources of error through implementation of an integrator followed by a track and hold circuit.

For condition (1) above, the signal POS is a logic "1" causing S3 to be closed to the input ANL POS which is an analog voltage representing the initial position. Through NOR1 and NOR2, S2 and S1 are closed, causing the output to rapidly slew to a value equal to the input ANL POS. For all remaining operations, the signal POS is held at a logic "0" which closes S3 between th...