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Duty Factor Model for CMOS Switching Power

IP.com Disclosure Number: IPCOM000050501D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Dearden, ZT: AUTHOR [+2]

Abstract

CMOS switching power depends strongly on duty factor (DF) amongst other parameters. A probabilistic model is disclosed for the CMOS switching DF for use in estimating the switching power in random logic.

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Duty Factor Model for CMOS Switching Power

CMOS switching power depends strongly on duty factor (DF) amongst other parameters. A probabilistic model is disclosed for the CMOS switching DF for use in estimating the switching power in random logic.

The model is presented for three-input NOR logic embodied in CMOS, but is easily extendable to other circuit configurations, and is derived from static or quiescent analysis.

From static analysis of randomly connected circuits, one can estimate P , the proportion of circuits which produce logic down levels at their outputs. The remaining proportion (1-P(0)=P(1) of circuits produce logic up levels at their outputs. For 3-input NOR logic, P(0)=2/3 P(1)=1/3.

Applied to a large ensemble of circuits, the quiescent probabilities P(0) and P(1) for the circuit output states apply before and after switching. Thus, for any one clock cycle of data processing internal to the chip during which the circuits can provide output logic transitions (no more than once per circuit per cyclg), the circuit switching or logic transition probability = 2 P(0)P(1)(=4/9, for 3-input NOR). Thus, for 3-input NOR, approx. 44 percent of the circuits are expected to switch once per cycle, an equal number of circuits changing states in either direction.

Switching DF is defined herein as the average number of transitions per circuit per cycle. DF = 2 P(0)P(1), provided logic state transition was the only mechanism. This is not generally the case, however, since before the circuit establishes valid logic transitions at sample time, they are likely to go through intermediate transitions commonly known as glitch transitions. Their contribution to the duty factor is described below.

Glitches may be generated as well as propagated. In either case, the circuit inputs may change, yet cause no stable change at the outputs (already included in 2P(0)P(1)). The glitch transition model is made tractable under the following assumptions and ...