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Electrostatic Discharge Susceptability Improvement in Capped Modules

IP.com Disclosure Number: IPCOM000050506D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Luce, AN: AUTHOR

Abstract

In modules with metal caps, the most sensitive damage path is between the input pin and the metal cap (isopotential external plane). The voltage at which electrostatic discharge (ESD) damage is likely to occur can be raised by increasing the distance between the metal cap and the chip/substrate package. This increased distance reduces the capacitive path between the pins and the isoplanar surface, reducing the amount of charge (electrostatic energy) passing through any one pin for a given ESD level (voltage). Satisfactory performance will be achieved at cap to chip/substrate distances greater than 0.6 cm.

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Electrostatic Discharge Susceptability Improvement in Capped Modules

In modules with metal caps, the most sensitive damage path is between the input pin and the metal cap (isopotential external plane). The voltage at which electrostatic discharge (ESD) damage is likely to occur can be raised by increasing the distance between the metal cap and the chip/substrate package. This increased distance reduces the capacitive path between the pins and the isoplanar surface, reducing the amount of charge (electrostatic energy) passing through any one pin for a given ESD level (voltage). Satisfactory performance will be achieved at cap to chip/substrate distances greater than 0.6 cm.

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