Browse Prior Art Database

Timing Analysis Model with Micro Block

IP.com Disclosure Number: IPCOM000050515D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Cheng, DD: AUTHOR [+3]

Abstract

Timing Analysis (TA) runs are preceded by steps in which all hardware logic is reduced to micro circuit blocks with delays. The following describes a means of marking the blocks with TA flags and the programs for interpreting the flags. These operate in such a way that it is possible to obtain the full TA modeling capability without losing any delay information.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Timing Analysis Model with Micro Block

Timing Analysis (TA) runs are preceded by steps in which all hardware logic is reduced to micro circuit blocks with delays. The following describes a means of marking the blocks with TA flags and the programs for interpreting the flags. These operate in such a way that it is possible to obtain the full TA modeling capability without losing any delay information.

Timing Analysis uses a set of flags which is defined for each block output. These flags are used to control the propagation (i.e., forward backward tracing) and tests (i.e., slack computation) of each block in the logic, including micro blocks of a storage element.

Each output pin contains three general fields: suffix, control flags for raising edge, and control flags for falling edge. Detailed descriptions of these fields follow.

Each suffix can have one or more levels depending on how many characters are present. The maximum number of levels in the suffix or flags at an output pin determines the number of replications which are made for that output (and the inputs feeding that output). However, an output must be replicated at least once.

The first character of the suffix (if not blank) at a pin is concatenated to the net name and an asterisk (*) to form a net name in the TA model for that pin in the first replication of the block. If there is no suffix, then nothing is concatenated. The second character of the suffix is similarly used in the second replication, if present, etc. If the second character is absent, then nothing is concatenated, etc.

Blocks are replicated because paths sometimes enter a block of a latch and feedback to the same block. If the blocks are not replicated, it is not possible to levelize the graph. Replication also allows different inputs to be passed to the outputs of the different replications.

The first set of flags (five characters) in "rise-flags" is used to control TA actions on the rising edge et the output of the first block replication.

The first set of "fall-flags" is similarly used for the falling edge. Successive sets are applied to the successive block replications, if they exist. Whenever a set of flags is not available, the value 'BBDNN' is assigned.

The fi...