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Handling of N-Cycle Paths and Race Conditions in Timing Analysis

IP.com Disclosure Number: IPCOM000050517D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Cheng, DD: AUTHOR [+4]

Abstract

This article is related to information contained in another article on pages 2819-2820 of this issue.

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Handling of N-Cycle Paths and Race Conditions in Timing Analysis

This article is related to information contained in another article on pages 2819-2820 of this issue.

The Timing Analysis algorithm is capable of checking all utilized paths in the logic. Every path starts at a path input (a storage element or a primary input) and ends at a path output (a storage element or a primary output). There are certain times at which a signal can enter a path at the path input. For an input to a storage element this would normally be any time a clock gates the storage element. Correspondingly, there are certain times by which the signal must reach the path output. For a storage element, this would normally be the next time a clock gates that storage element.

Timing Analysis checks every path to see if a signal entering a path reaches the output by the required path output time. This timing verification is independent of logic function and also assumes that basically all paths can be analyzed within one clock cycle of the machine.

There may be, however. a number of paths in the logic which are designed to take two or more cycles to complete the path transition. These paths are dependent on the logic functions along the paths to provide gating of signals. Since Timing Analysis does not take block functions into account (except for inversion property), these 2-cycle paths would not be correctly analyzed. Some examples of 1-cycle paths (independent of block function) and 2-cycle paths (dependent on block function) are shown in Fig. 1.

The technique presented here would allow Timing Analysis to handle a 2- cycle path by editing into the path an extra block which is assigned a negative delay value or by modifying the delay on...